1. Field of the Invention
The present invention relates to data transfer control circuitry for use in, e.g. a personal computer (PC) card interface (IF), for controlling the transfer of data between a host computer and a local processor.
2. Description of the Background Art
Conventionally, a PHS (Personal Handyphone System) data communication card, for example, regulated in Japan is a peripheral to be inserted in the card receptacle slot of a host computer assigned to a PC card, thereby allowing the host computer to access to the Internet. The PHS card satisfies the PCMCIA (Personal Computer Memory Card International Association) standards. The PCMCIA standards, originally proposed as an interface for semiconductor memory cards, prescribe address and data signal requirements to allow data to be transferred between a host computer and a PC card in the form of parallel signals.
The PHS card includes a memory card interface based on the PCMCIA standards to be received by the card slot of, and connected to, the host computer. The memory card interface decodes an address signal, and transfers data and control signals between the host computer and a UART (Universal Asynchronous Receiver-Transmitter) circuit, which is also included in the PHS card.
The UART circuit is interconnected to a microprocessor functioning as a local processor in the PHS card, and converts parallel data input from the memory card interface on a byte basis to a character-by-character serial signal, adds start and stop sync bits to the leading and tailing ends of a character code signal to transfer the resulting signal at a certain transfer rate. Also, the UART circuit converts a character-by-character signal with start and stop sync bits input thereto in serial from the microprocessor to byte-by-byte parallel signals to deliver the parallel signals to the memory card interface.
The microprocessor also includes a corresponding UART circuit configured to convert the serial signal input from the card interface to parallel signals and parallel signals to be output to the card interface to a serial signal. The PHS communication card additionally includes a radio transmitter-receiver, or duplexer.
When the host computer feeds the PHS data communication card with data to be transmitted, the UART circuit converts the input parallel data to a corresponding serial signal at the transfer rate to deliver the serial signal to the microprocessor. In the microprocessor, the corresponding UART circuit transforms the input serial signal to parallel signals, which are in turn stored in a temporary memory. The parallel signals are ultimately transmitted by the radio duplexer from an antenna on a radio wave.
On the other hand, a radio wave signal caught by the antenna is converted to received data through the radio duplexer to be temporarily stored in the temporary memory by the microprocessor. Subsequently, the UART circuit of the microprocessor converts the received data to a corresponding serial signal at the transfer rate to be transferred to the other UART circuit. The latter UART circuit converts the input serial signal to parallel signals, or received data, and delivers the parallel signals to the host computer via the memory card interface.
The PHS card thus includes the local processor and the memory card interface which are interconnected to each other by the pair of UART circuits. The UART circuits interchange serial data at the transfer rate in time with a clock signal CLK. The host computer can thus transmit and receive data to and from another computer via the PHS telecommunications system at the timing and under the protocol prescribed to the system.
However, the conventional PHS data communication card with the above-stated configuration has the following problem left unsolved. In order to match the data transfer timing between the host and other computers, the pair of UART circuits on the PHS card interchange data therebetween in the form of serial signals. It is therefore necessary between the pair of UART circuits to convert parallel data to be transmitted or received to a serial signal and again convert the serial signal to parallel data. Those two conversion stages make data transfer control circuitry including the UART circuits sophisticated while aggravating power consumption ascribable to the data conversion.